MPC8360ZUAGDGA中文资料PowerQUICC, 32 Bit Power Arch SoC, 400MHz, DDR1/2, PCI, 1GbE, USB, TDM, ATM, 0 to 105C, Rev 1数据手册恩XP规格书

描述 Description

Our MPC8360E PowerQUICC® II Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line containing cores built on Power Architecture® technology. The MPC8360E family incorporates a next-generation communications engine, the QUICC Engine®. supporting a wide range of protocols, including Gigabit Ethernet (GbE) and OC-12 asynchronous transfer mode (ATM)/packet over SONET (POS). Additional enhancements include the e300 core (enhanced version of the 603e™ core with larger caches), scaling up to 667 MHz, a double data rate (DDR) memory controller and the integrated security engine.
The MPC8360E PowerQUICC II Pro communications processor's advanced features make it suitable for today and tomorrow's wired and wireless access equipment, as well as small and medium enterprise networking equipment. Target applications include multitenant units (MTUs), DSL access multiplexers (DSLAMs), wireless basestations, multi-and fixed-subscriber access nodes, add/drop multiplexers and routers.
The MPC8358E processor, a member of the MPC8360E PowerQUICC II Pro family, is pin-compatible with the MPC8360E. The MPC8358E offers a cost-effective, low-power processing solution that meets the performance requirements for broadband access applications, such as small-to-medium enterprise (SME) routers, low-end DSLAMs and IP private automatic branch exchange (PABX) systems.
e300 System-on-Chip PlatformThe MPC8360E PowerQUICC II Pro family is based on the e300 system-on-chip (SoC) platform. This makes it easy and fast to add or remove functional blocks and develop additional SoC-based family members for emerging markets. At the heart of the e300 SoC platform is Our e300 core built on Power Architecture technology. The e300 core is an enhanced version of the 603e core used in previous-generation PowerQUICC II processors.
Enhancements include twice as much L1 cache (32 KB data cache and 32 KB instruction cache) with integrated parity checking and other performance-enhancing features. The e300 core is software-compatible with existing 603e core-based products.
ConnectivityThe MPC8360E processor is designed to support a wide range of communications interfaces, such as MII, RMII, GMII, TBI, RTBI, NMSI, UTOPIA, POS and TDM. The dual 32-bit DDR memory controllers help to ensure high-speed memory access and a local system bus operating up to 133 MHz. Additional system connectivity is supplied by dual UART, dual inter-integrated circuit (I²C), dual serial peripheral interface (SPI), PCI interfaces and universal serial bus (USB) interface (USB 2.0 full-/low-speed compatible).
Integrated SecurityThe MPC8360E and MPC8358E processors feature integrated security with the powerful integrated security engine derived from Our security coprocessor product line. Integrated security supports DES, 3DES, MD-5, SHA-1, AES and ARC-4 encryption algorithms, as well as a public key accelerator and an on-chip random number generator. The integrated security engine is capable of single-pass encryption and authentication, as required by IPsec, the IEEE® 802.11i standard and other security protocols.
Typical Applications

特性 Features

• e300 core operating from 266 MHz to 667 MHz
• 32-bit, high-performance superscalar core
• Double-precision floating point, integer, load/store, system register branch processor units and 32 KB data and 32 KB instruction cache with line-locking support
• Two 32-bit RISC controllers for flexible support of the communications peripherals
• 10/100/1000 Mbps Ethernet
• Inverse multiplexing for ATM (IMA)
• Transparent
• Multilink, multiclass PPP
• UART
• One multichannel communication controller (MCC) supporting
• 256 channels with up to eight TDMs
• Support for signaling system number 7 (SS7)
• Two UTOPIA/POS interfaces supporting up to 128 multi-PHY each
• Eight TDM interfaces (T1/E1)
• Aggregate bandwidth of 64 kbps and 256 channels
• 2,048 bytes of SI RAM (1,024 entries)
• Bit or byte resolution
• Supports T1, CEPT, T1/E1, T3/E3, pulse-code modulation highway, ISDNprimary/basic rate, NXP® interchip digital link (IDL) and user-defined TDM serial interfaces
• Four independent 16-bit timers that can be interconnected as two 32-bit timers
• USB interface (USB 2.0 full-/low-speed compatible)
• Programmable timing supporting both DDR1 and DDR2 SDRAM
• Four banks of memory, each up to 1 GB
• PCI interface
• One 32-bit PCI 2.2 bus controller (3.3V I/O; up to 66 MHz)
• Public key execution (RSA and Diffie-Hellman)
• Advanced encryption standard (AES) execution
• Message digest execution (SHA, MD5, HMAC)
• Local bus controller
• Multiplexed 32-bit address and data operating up to 133 MHz
• Dual UART (DUART)
• Four-channel DMA controller
• IEEE 1149.1 JTAG test access port
• Process technology: 130 nm CMOS
• This product is included in NXP’s product longevity program, with assured supply for a minimum of 10 years after launch

应用 Application

Secure Transaction and Retail Payments
•POS Printer