PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications

This document provides an overview of the MPC8358E PowerQUICC II Pro processor revision 2.1 PBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking,

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恩XP

PowerQUICC, 32 Bit Power Arch SoC, 400MHz, DDR1/2, PCI, 1GbE, USB, TDM, ATM, SEC, -40 to 105C, Rev 1

NXP® Semiconductors's MPC8360E PowerQUICC® II™ Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line containing cores built on Power Architecture technology. The MPC8360E family incorporates a next-generation communications engine, the QU DDR memory controller• Programmable timing supporting DDR-1 and DDR-2 SDRAM\n• 2 x 32-bit or 1 x 64-bit data interface; up to 266 MHz data rate\n• Four banks of memory, each up to 1 GB\n• Full ECC support;

恩XP

恩智浦

MPC8360E/MPC8358E PowerQUICC II Pro Processor

文件：617.94 Kbytes 页数：102 Pages

freescaleFreescale Semiconductor, Inc

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PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications

文件：612.19 Kbytes 页数：102 Pages

freescaleFreescale Semiconductor, Inc

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