MPC8265AZUPIBC中文资料POWER QUICC II HIP4C数据手册恩XP规格书

描述 Description

The PowerQUICC® II™ integrated communications processor family delivers excellent integration of processing power for networking and communications peripherals, providing customers with an innovative, total system solution for building high-end communications systems. NXP® Semiconductors's PowerQUICC II processor family is the next generation of the leading PowerQUICC™ line of integrated communications processors, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.
Our leading PowerQUICC architecture integrates two processing blocks. One block is a high-performance embedded G2 core and the second block is the Communications Processor Module (CPM). The CPM of the PowerQUICC II processor can support up to three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the PowerQUICC II processor family, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.

特性 Features

Product Highlights
• Powerful memory controller and system functions
• Up to three multiport 10/100 Mbps ethernet MAC
• Up to 256 HDLC channels (each channel 64 Kbps, full duplex)
• Transmission convergence sub-layer and inverse multiplexing for ATM capabilities
• Strong 3rd-party tools support from 恩智浦合作伙伴计划 partner program members
• Remote Access Concentrators
• Cellular Infrastructure equipment
• Ethernet Switches
• xDSL Systems
• Embedded G2 core available from 133 - 300 MHz
• 190 MIPS at 100 MHz (Dhrystone 2.1)
• 570 MIPS at 300 MHz (Dhrystone 2.1)
• Disable CPU mode
• Improved low-power core
• Memory Management Unit
• Common On-chip Processor (COP)
• Memory controller, including two dedicated SDRAM machines
• Hardware bus monitor and software watchdog timer
• High-Performance CPM with operating frequency up to 133, 166, or 200 MHz
• G2 core and CPM may run at different frequencies
• On-board 32 KBytes of dual-port RAM
• Virtual DMA functionality
• Up to 155 Mbps ATM SAR (maximum of two) (AAL0, AAL1, AAL2,AAL5)
• 45 Mbps HDLC / Transparent (up to three)
• Three MII interfaces
• Transmission Convergence Layer capabilities
• Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus
• Integrated PCI interface
• 300 MHz power consumption: 2.5 W
• IMA/TC layer functionality
• Integrated PCI capability

应用 Application

Secure Transaction and Retail Payments
•POS Printer