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MPC603EXXXXXXX中文资料PDF规格书
MPC603EXXXXXXX规格书详情
Features
This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major features
of the 603e are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast-trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
• Integrated power management
— Low-power 3.3-volt design
— Internal processor/bus clock multiplier that provides 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1
ratios
— Three power saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
FREESCALE |
23+ |
NA/ |
358 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
FREESCALE |
2016+ |
BGA |
6528 |
只做进口原装现货!假一赔十! |
询价 | ||
MOTOROLA/摩托罗拉 |
/ |
BGA |
27 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
FREESCALE |
2022 |
BGA |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
MOTOROLA/摩托罗拉 |
BGA |
899933 |
集团化配单-有更多数量-免费送样-原包装正品现货-正规 |
询价 | |||
MOTOROLA |
22+ |
BGA |
3000 |
原装正品,支持实单 |
询价 | ||
MC |
23+ |
CPU |
4500 |
全新原装、诚信经营、公司现货销售! |
询价 | ||
MC |
23+ |
CPU |
2500 |
绝对全新原装!现货!特价!请放心订购! |
询价 | ||
FREESCAL |
23+ |
BGA |
19726 |
询价 | |||
FREESCALE |
BGA |
265209 |
假一罚十原包原标签常备现货! |
询价 |