MPC566MZP56中文资料NXP 32-bit MCU, Power Arch core, 1MB Flash, 56MHz, -40/+125degC, Automotive Grade, PBGA 388数据手册恩XP规格书

描述 Description

The MPC566 integrates a Power Architecture® core with a dual precision floating point unit and BCC, 36 KB of RAM and 1 MB of flash memory.
The MPC566, an upgraded version of the MPC565, offers code compression to enable more efficient use of internal or external flash memory. Code compression is optimized for automotive (non-cached) applications and the new scheme increases performance by 40 to 50 percent.

特性 Features

• Supports code compression
• Three time processor units (TPU3)
• TPU3_A and TPU3_B are connected to DPTRAM_AB (6 KB)
• TPU3_C is connected to DPTRAM_C (4 KB)
• A 22-timer channel modular I/O system (MIOS14)
• Same as MIOS1 plus a real-time clock sub-module (MRTCSM), four counter sub-modules (MCSM), and four pulse width modulated (PWM) sub-modules (MPWMSM)
• Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
• Two enhanced queued analog-to-digital converters (QADC64E_A, QADC64E_B) with up to 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part (orthogonal)
• Two queued serial multi-channel module (QSMCM_A, QSMCM_B), each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
• A J1850 (DLCMD2) communications module
• A NEXUS debug port (class 3) – IEEE®-ISTO 5001-1999
• JTAG and background debug mode (BDM)