MPC185中文资料Security Processor数据手册恩XP规格书

描述 Description

Overview The MPC185 security processor is a powerful addition to any networking or computing system supporting the 60x bus protocol. It is designed to off-load computational intensive security functions, such as key generation and exchange, authentication and bulk encryption from processors such as Our PowerQUICC® II™ communications processors or any PowerPC processor. Typical applications include edge routers, DSLAMS, broadband access equipment, e-commerce servers, wireless base stations, and WAP gateways.
Archived content is no longer updated and is made available for historical reference only.
Archived content is no longer updated and is made available for historical reference only.

特性 Features

\t•2 Public key execution units (PKEUs) that support the following:
\t\t
\t\t\t•RSA and Diffie-Hellman

\t\t\t•Programmable field size up to 2048 bits

\t\t\t•Elliptic curve cryptography

\t\t\t•F2m and F(p) modes

\t\t\t•Programmable field size up to 511 bits

\t\t
\t

\t•2 Data Encryption Standard execution units (DEUs)
\t\t
\t\t\t•DES, 3DES

\t\t\t•Two key (K1, K2, K1) or Three key (K1, K2, K3)

\t\t\t•ECB and CBC modes for both DES and 3DES

\t\t
\t

\t•2 Advanced Encryption Standard units (AESU)
\t\t
\t\t\t•Programmable key length of 128, 192, or 256 bits

\t\t\t•Implements the Rinjdael symmetric key cipher

\t\t\t•Support for ECB, CBC, and counter modes

\t\t
\t

\t•1 ARC Four execution unit (AFEU)
\t\t
\t\t\t•Implements a stream cipher compatible with the RC4 algorithm

\t\t\t•40- to 128-bit programmable key

\t\t
\t

\t•2 Message digest execution units (MDEUs)
\t\t
\t\t\t•SHA-1 with 160-bit message digest or SHA-2 with 256-bit message digest

\t\t\t•MD5 with 128-bit message digest

\t\t\t•HMAC with any algorithm

\t\t
\t

\t•1 Kasumi execution unit for 3GPP systems (KEU)
\t\t
\t\t\t•Implements F8 algorithm for encryption and F9 algorithm for authentication

\t\t
\t

\t•1 Random number generator (RNG)

\t•60x compliant external bus interface, with master/slave logic
\t\t
\t\t\t•32-bit address/64-bit data

\t\t\t•Up to 100 MHz operation

\t\t
\t

\t•4 Crypto-channels, each supporting multi-command descriptor chains
\t\t
\t\t\t•Static and/or dynamic assignment of crypto execution units via an integrated controller

\t\t\t•Buffer size of 2 KB for each execution unit, with flow control for large data sizes

\t\t
\t

\t•32 KB of internal scratchpad memory for key, IV and context storage

\t•1.5V supply, 3.3V and 2.5V I/O

\t•256 MAP BGA, 17 x 17mm package body size

\t•1.5W power dissipation

\t•Software and development support available