MMC2001中文资料32-Bit Microcontroller数据手册恩XP规格书

描述 Description

Overview The 32-bit MMC2001 integrated processor is a charter member of the M·CORE family of microcontrollers. Representing a new vision in 32-bit microRISC processors, the M·CORE architecture delivers the power-sensitive, cutting-edge interrput/system performance that our customers demand. The processor architecture has been designed for high-performance, cost-sensitive embedded control applications, with particular emphasis on reduced system power consumption, making the MMC2001 ideal for battery-operated, portable products such as GPS, handheld industrial/medical instrumentation, cameras, industrial controllers, and others. Ultra-low power and amazing performance The M·CORE processors gives customers best-in-class power consumption from an entirely new instruction set with standard peripherials. Running on a supply voltage between 1.8 to 3.6 volts, the new device achieves sustained performance of 31 Drhy 2.1 MIPS at an internal clock speed of 33 MHz. Archived content is no longer updated and is made available for historical reference only.

特性 Features

•M·CORE™ Integer Processor
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\t•32-bit RISC architecture
\t•Low power, high performance
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•On-chip, 256-Kbyte ROM
•On-chip, 32-Kbyte SRAM with battery backup supply support
•Interrupt Controller
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\t•Support for up to 32 interrupt sources
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•External Interface Module (EIM)
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\t•Transfers information between the MMC2001 and external memory or periph-erals
\t•20 address lines
\t•16 data lines
\t•Chip select and wait state generation
\t•Bus watchdog timer
\t•Timer/Reset Module
\t•Crystal oscillator: generates the master clock signal for the time-of-day timer from a 32.768-kHz external crystal
\t•Time-of-day timer: provides time-of-day information as well as an alarm clock function
\t•Watchdog timer: resets the chip to recover from system failure
\t•Reset unit: provides low voltage detection input and backup power switching for SRAM and the time-of-day timer
\t•Periodic interrupt timer
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•Universal Asynchronous Receiver/Transmitter Module (UART)
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\t•Two independent UART channels
\t•Asynchronous operation
\t•Baud rate generation
\t•Infrared (IR) interface support
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•16-bit general-purpose I/O port with support for keyboard scan/encode
•8-bit general-purpose I/O port with support for edge/level sensitive external inter-rupts
•Pulse-Width Modulation Module (PWM)
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\t•Six independent PWM channels
\t•Programmable period
\t•Programmable duty cycle
\t•Periodic interrupt capability
\t•Pins can be configured as general-purpose I/O
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•Interval Mode Serial Peripheral Interface (ISPI)
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\t•Efficient communication with slower serial peripherals
\t•Designed for master/slave SPI operation
\t•Interval-mode SPI operation
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•OnCE™ Debug Module