Dual J-K Flip-Flops with Clear

文件：140.08 Kbytes 页数：6 Pages

NSC

国半

Dual J-K Flip-Flops with Clear

General Description\nThese J-K Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power dissipation of standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads.\nThese flip-flops are edge sensitive to the clock input and change st ■ Typical propagation delay: 16 ns\n■ Wide operating voltage range: 2–6V\n■ Low input current: 1 mA maximum\n■ Low quiescent current: 40 mA (74HC Series)\n■ High output drive: 10 LS-TTL loads ;

TI

德州仪器

Dual J-K Flip-Flops with Clear

文件：140.08 Kbytes 页数：6 Pages

NSC

国半

DUAL J.K FLOPS WITH CLEAR

文件：123.49 Kbytes 页数：4 Pages

TI

德州仪器