3-to-8 Line Decoder With Address Latches

文件：151.97 Kbytes 页数：6 Pages

NSC

国半

3-to-8 Line Decoder With Address Latches

General Description\nThese devices utilize advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains ■ Typical propagation delay: 20 ns\n■ Wide supply range: 2–6V\n■ Latched inputs for easy interfacing\n■ Fanout of 10 LS-TTL loads ;

TI

德州仪器

3-to-8 Line Decoder With Address Latches

文件：151.97 Kbytes 页数：6 Pages

NSC

国半

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

文件：129.24 Kbytes 页数：6 Pages

TI

德州仪器

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

文件：129.24 Kbytes 页数：6 Pages

TI

德州仪器

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

文件：116.41 Kbytes 页数：5 Pages

TI

德州仪器