MM54C08J数据手册TI中文资料规格书

描述 Description

General Description
Employing complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin, these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.

特性 Features

■ Wide supply voltage range 3.0V to 15V
■ Guaranteed noise margin 1.0V
■ High noise immunity 0.45 VCC (typ.)
■ Low power Fan out of 2
   TTL compatibility driving 74L
■ Low power consumption 10 nW/package (typ.)