MK3720数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The MK3720D is a drop-in replacement for the MK3720S and MK3720A devices. Compared to these earlier devices, the MK3720D offers a wider operating frequency range and improved power supply noise rejection.The MK3720 is a low cost, low jitter, high-performance 3.3 volt VCXO and PLL clock synthesizer designed to replace expensive 13.5, 27, or 54 MHz VCXOs. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by ±100 ppm. Using our patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive external 13.5 MHz pullable crystal input to produce output clocks of 13.5 MHz, 27 MHz, and 54 MHz.The MK3720D exhibits a moderate VCXO gain of 120 ppm/V typical, when used with a high-quality external pullable quartz crystal.The frequency of the on-chip VCXO is adjusted by an external control voltage input into pin VIN. Because VIN is a high impedance input, it can be driven directly from a PWM RC integrator circuit.

特性 Features

MK3720D is a drop-in upgrade to the earlier MK3720S and MK3720A devices
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Operating voltage 3.3 V (±5%)
Output clocks of 54, 27, and 13.5 MHz
Uses an inexpensive 13.5 MHz external crystal
On-chip patented VCXO with pull range of 200 ppm (minimum)
VCXO tuning voltage of 0 to 3.3 V
12 mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
MK3720D is recommended for new designs