3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

文件：143.16 Kbytes 页数：6 Pages

ICST

3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

Features • Clock outputs from 10 to 133 MHz • Zero input-output delay • Eight low skew (

文件：354.31 Kbytes 页数：9 Pages

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3.3V Zero Delay, Low Skew Buffer

The MK2308-1H is a low phase noise, high-speed PLL based, 8-output, low skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero d ·Clock outputs from 10 to 133 MHz\n·Zero input-output delay\n·Eight low skew (<200 ps) outputs\n·Device-to-device skew <700 ps\n·Full CMOS outputs with 25 mA output drive capability at TTL levels\n·5 V tolerant FBIN and CLKIN pins\n·Tri-state mode for board-level testing\n·Advanced, low-power, sub-m;

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3.3V ZERO DELAY CLOCK MULTIPLIER

文件：171.99 Kbytes 页数：13 Pages

IDT

3.3V ZERO DELAY CLOCK MULTIPLIER

文件：171.99 Kbytes 页数：13 Pages

IDT

3.3V ZERO DELAY CLOCK MULTIPLIER

FEATURES: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the cl

文件：309.08 Kbytes 页数：14 Pages

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