MK2069-03GI中文资料瑞萨数据手册PDF规格书

Features

• Wide range VCXO PLL feedback divider allows high

frequency multiplication ratios and the input of very low

input reference frequencies

• Input clock frequency of <1kHz to 27MHz

• Output clock frequency of 500kHz to 160MHz

• PLL lock status output

• VCXO-based clock generation offers very low jitter and

phase noise generation, even with low frequency or jittery

input clock.

• PLL Clear function (CLR input) allows the VCXO to

free-run, offering a short term holdover function.

• 2nd PLL provides frequency translation of VCXO PLL to

higher or alternate output frequencies.

• Device will free-run in the absence of an input clock (or

stopped input clock) based on the VCXO frequency

pulled to minimum frequency limit.

• Low power CMOS technology

• 56-pin TSSOP package

• Single 3.3V power supply