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MIMXRT1166CVM5A中文资料恩XP数据手册PDF规格书

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厂商型号

MIMXRT1166CVM5A

功能描述

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products

文件大小

3.20532 Mbytes

页面数量

130

生产厂商

恩XP

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-10-4 23:00:00

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MIMXRT1166CVM5A规格书详情

The i.MX RT1160 processors are based on Arm Cortex®-M7 Core™ Platform, which has the following

features:

• The Arm Cortex-M7 Core Platform:

— 32 KB L1 Instruction Cache and 32 KB L1 Data Cache

— Floating Point Unit (FPU) with single-precision and double-precision support of Armv7-M

Architecture FPv5

— Support the Arm®v7-M Thumb instruction set, defined in the Armv7-M architecture

— Integrated Memory Protection Unit (MPU), up to 16 individual protection regions

— Up to 512 KB I-TCM and D-TCM in total

— Frequency of 500 MHz

— ECC support for both cache and TCM

— Frequency of the core, as per Table 11, Operating ranges, on page 27.

• The Arm Cortex®-M4 Core platform:

— Cortex-M4 processor with single-precision FPU defined by Armv7-M architecture FPv4-SP

— Integrated MPU with 8 individual protection regions

— 16 KB Instruction Cache, 16 KB Data Cache, and 256 KB TCM

— Frequency of 240 MHz

— ECC support for TCM and parity check support for cache

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