MH2S64CWZTJ-15中文资料三菱电机数据手册PDF规格书

DESCRIPTION

The MH2S64CZTJ/CWZTJ is 2097152-word by 64-bit Synchronous DRAM module. This consists of eight industry standard 2Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.

The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.

This is a socket type - memory modules, suitable for easy interchange or addition of modules.

FEATURES

• Utilizes industry standard 2M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP

• 168-pin (84-pin dual in-line package)

• single 3.3V±0.3V power supply

• Clock frequency 83MHz/67MHz

• Fully synchronous operation referenced to clock rising edge

• Dual bank operation controlled by BA(Bank Address)

• /CAS latency- 1/2/3(programmable)

• Burst length- 1/2/4/8(programmable)

• Burst type- sequential / interleave(programmable)

• Column access - random

• Auto precharge / All bank precharge controlled by A10

• Auto refresh and Self refresh

• 4096 refresh cycle /64ms

• LVTTL Interface

APPLICATION

main memory or graphic memory in computer systems