MCXA133VFT中文资料恩XP数据手册PDF规格书

Features

• Arm Cortex-M33 48MHz(A14x) or 96MHz(A15x, A13x) with 381

CoreMark (3.97 CoreMark/MHz)

• Up to 128 KB Flash, 32 KB SRAM, up to 8 KB SRAM with ECC

• All RAM can be retained down to Deep Power Down mode

• -40 °C to 125 °C temperature range

• Down to 53 μA/MHz active current, 6.5 μA Power Down mode with all

SRAM retntion 394 nA Deep Power Down current

Core

• Arm 32-bit Cortex-M33 CPU, no FPU, no DSP extension instruction set,

no TrustZone, no MPU

Memories

• Single-bank Flash: Up to 128 KB FLASH with ECC (support one bit correction and two bits detection)

• Cache Engine with 4 KB RAM

• Up to 32 KB RAM, configurable as up to 8 KB RAM with ECC (support single bit correction, two bits detection)

• All RAM can be retained down to Deep Power Down mode

• 16 KB ROM

Security

• 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version 5 specification

• Device lifecycle management

• Flash read/write/execute permission protect by MBC and lockable

• Implicit-protected Flash Region (IFR)

• Security Monitoring

— Code Watchdog for code flow integrity checking

— GLIKEY enhances protection against attacks to gain unauthorized access to sensitive registers

Low-Power Performance

• Active: 53 μA/MHz in Active Mode (While(1) executing from flash, 3.3 V @25 °C )

• Deep Sleep: 20.28 μA, 7.4 μs wake-up ( 3.3 V @25 °C)

• Power Down: 6.5 μA, 17.1 μs wake-up (full SRAM retention, 3.3 V@ 25 °C)

• Deep Power Down: 394 nA, 2.36 ms wake-up (wake timer disabled, reset pin enabled, all SRAM off, 3.3 V @25 °C)

System and Clocks

• 192 MHz MHz free-running oscillator (FRO192M)

• 12 MHz free-running oscillator (FRO12M)