MCM69T618TQ5R中文资料摩托罗拉数据手册PDF规格书

The MCM69T618 is a 1M–bit synchronous fast static RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB secondary cache as well as to be used as a data RAM for 512KB caches. This device is organized as 64K words of 18 bits each. It integrates input registers, output registers, tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache tag RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle

• Single 3.3 V + 10, – 5 Power Supply

• Pipelined Data Comparator

• Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path

• 64K x 18 Organization Supports Up to 2MB Cache

• Synchronous Data Input Register Load Enable (DE)

• Internally Self–Timed Write Cycle

• Asynchronous Data I/O Output Enable (G)

• Asynchronous Match Output Enable (MG)

• 100–Pin TQFP Package