MCM69F618C中文资料摩托罗拉数据手册PDF规格书

64K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM

The MCM69F618C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, 486, i960, and Pentium microprocessors. It is organized as 64K words of 18 bits each. This device integrates input registers, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

For read cycles, a flow–through SRAM allows output data to simply flow freely from the memory array.

The MCM69F618C operates from a 3.3 V power supply and all inputs and outputs are LVTTL compatible and 5 V tolerant

• MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle

MCM69F618C–9 = 9 ns Access / 12 ns Cycle

MCM69F618C–10 = 10 ns Access / 15 ns Cycle

MCM69F618C–12= 12 ns Access / 16.6 ns Cycle

• Single 3.3 V + 10, – 5 Power Supply

• ADSP, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• 5 V Tolerant on all Pins (Inputs and I/Os)

• 100–Pin TQFP Package