MCM62110FN15中文资料摩托罗拉数据手册PDF规格书

32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check. This device has increased output drive capability supported by multiple power pins. In addition, the output levels can be either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power supply.

The MCM62110 is available in a 52–pin plastic leaded chip carrier (PLCC).

This device is ideally suited for pipelined systems and systems with multiple data buses and multiprocessing systems, where a local processor has a bus isolated from a common system bus.

• Single 5 V ± 10 Power Supply

• Choice of 5 V or 3.3 V ± 10 Power Supplies for Output Level Compatibility

• Fast Access and Cycle Times: 15/17/20 ns Max

• Self–Timed Write Cycles

• Clock Controlled Output Latches

• Address, Chip Enable, and Data Input Registers

• Common Data Inputs and Data Outputs

• Dual I/O for Separate Processor and Memory Buses

• Separate Output Enable Controlled Three–State Outputs

• Odd Parity Checker During Reads

• Open Drain Output on Data Parity Error (DPE) Allowing Wire–ORing of Outputs

• High Output Drive Capability: 85 pF/Output at Rated Access Time

• High Board Density 52 Lead PLCC Package

• Active High and Low Chip Enables for Easy Memory Depth Expansion

• Can be used as Separate I/O x9