MCDP5200B0T中文资料芯凯电子数据手册PDF规格书

Features

• USB Type-C DisplayPort Alt-mode de-mux

 Simultaneous USB3.1 Gen2 and 2 lanes DP1.4a

input OR 4 lanes DP1.4a input

 Flip option for connector plug orientation

 DP lane swap and polarity swap

• DisplayPort® (DP) ver.1.4a compliant receiver

 Link rate 1.62 / 2.7 / 5.4 / 8.1Gbps

 1, 2, or 4 lanes configuration

 AUX CH 1Mbps

 HPD_OUT

 Programmable receiver equalization

 TPS4 EQ Phase LT support

 Scrambling of main link data

 De-spreading of link frequency

 Video Stream Handling

■ RGB/ YCC 444/422/420 pixel format up to 16 bpc

 DPCD and CEC

■ DPCD data structure revision 1.4

■ CEC tunneling over AUX

 Audio stream handling

■ Non-HBR Compressed Formats

• 2/8 ch layouts

• Up to 192kHz sample rates

• Dolby Digital, Digital+, Atmos

■ HBR Audio Formats

• 8 ch layout

• Up to 1536kHz sample rates

• Dolby TrueHD, Atmos, DTS Master

■ LPCM Formats2/8/16/32 Ch

• Up to 192kHz sample rates

• 3D LPCM, speaker allocation & mapping

■ One Bit DSD Formats

• 2/8 ch

• Single & Double Rate

• 12288kHz sample rates

■ DST DSD Formats

• Single/Double rate

• Up to 22579.2kHz

• Audio InfoFrame/ ACM/ ISRC/ Audio

Metadata DI packets

• HDMI2.0b transmitter

 HDMI mode

■ DC-coupled output with source termination

■ 600 MHz maximum TMDS character clock

■ TMDS character-clock divide_by_4 mode

■ HPD_IN (5V Tolerant)

■ DDC CH (5V Tolerant)

■ Conversion to DVI output

 Scrambler for HDMI output

 Programmable signal amplitude

 Programmable pre-emphasis control

 Pixel format RGB / YCC 444/422/420

 Deep color up to 16 bits per color

 3D video timings

 CEC 2.0+ with snooping, tunneling

 SCDC read request handling

 Metadata handling

• HDMI 2.1 Features

 Through 6GHz TMDS Mode

 Supports 4k120Hz,4:2:0, 8bpc with Adaptive Sync

to VRR conversion

 Dynamic HDR Metadata through Extended

Metadata Packet

 Supports VRR, FVA, QMS, QFT, ALLM

• USB3.1 compliant re-timer

 5Gbps and 10Gbps support

 Spread spectrum clocking

 LFPS polling and processing

 Lane polarity inversion

 Bit level re-timer for SS mode

 SRIS (Separate Reference Clock Independent

SSC) for SSP mode

 Adaptive Receiver Equalization

 Multi-tap FIR EQ Transmitter Emphasis