MC9S12XDT512CAA

9S12XDT512 TSMC3 GENERAL; • 16-bit HCS12X CPU• Upward compatible with HCS12 instruction set\n• Interrupt stacking and programmer's model identical to HCS12\n• Instruction queue\n• Enhanced indexed addressing\n• Enhanced instruction set\n• EBI (external bus interface)\n• MMC (module mapping control)\n• INT (interrupt controller)\n• DBG (debug module to monitor HCS12X CPU and XGATE bus activity)\n• BDM (background debug mode)\n• XGATE • Peripheral coprocessor\n• Parallel processing module offloads the CPU by providing high-speed data processing transfer between peripheral modules, RAM and I/O ports\n• Data transfer between flash EEPROM, peripheral modules and I/O ports\n• Enhanced MSCAN module delivers full CAN performance with virtually unlimited number of mailboxes when used with XGATE\n• Phase-lock loop (PLL) circuit allows power consumption and performance to be adjusted to suit operational requirements; system power consumption can be further improved with \"fast exit from stop mode\" feature\n• I/O ports available in each module and up to 25 additional I/O ports are available with interrupt capability allowing wake-up from stop or wait mode\n;

Targeted for automotive multiplexing and mid-range body applications requiring flash from 64 KB to 512 KB, the MC9S12XD family gives you 32-bit performance (up to 80 MHz) with all the advantages and efficiencies of a 16-bit MCU.\nThe S12X provides low power consumption, excellent electromagnetic compatibility performance and code-size efficiency advantages.\n

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MC9S12XDT512CAA

S12XD, S12XB & S12XA Families

MC9S12XDT512

HCS12XMicrocontrollers

MC9S12XDT512

Covers,S12XD,S12XB&S12XAFamilies

MC9S12XDT512CAA

NXP
QFP80

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