MC9S12UF32PB中文资料飞思卡尔数据手册PDF规格书

Overview

The MC9S12UF32 microcontroller unit (MCU) is USB2.0 device for memory card reader and ATA/ATAPI interface applications. This device is composed of standard on-chip modules including a 16-bit central processing unit (HCS12 CPU), 32k bytes of Flash EEPROM, 3.5k bytes of RAM, USB2.0 interface, Integrated Queue Controller (IQUE) block with 1.5k bytes RAM buffer for USB Bulk data transport, ATA5 interface, Compact Flash interface, SD/MMC interface, SmartMedia interface, Memorystick interface, a 16-bit 8-channel timer, Serial Communication Interface, 73 discrete digital I/O channels and 2 input only channels1. The MC9S12UF32 has full 16-bit internal data paths throughout.

特性 Features

• HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.Instruction queue

iv. Enhanced indexed addressing

– Multiplexed External Bus Interface (MEBI)

– Memory Mapping Control (MMC)

– Interrupt Control (INT)

– Single-wire Background Debug Mode (BDM)

– On-chip hardware Breakpoints (BKP)

• Clock and Reset Generator (CRG_U)

– Clock Throttle to prescale the oscillator clock or 60Mhz clock from USB20D6E2F.

– COP watchdog

– Real Time Interrupt

• Memory

– 32K Flash EEPROM

- Internal program/erase voltage generation

- Security and Block Protect bits

– 3.5K byte RAM

- Used as a contiguous 3.5k byte SRAM with misaligned access support

- Configurable to 1084 byte SRAM and 2000 x 10 bit SRAM for Smartmedia logical to physical address translation and parity generation/checking support.

– 1.5K byte Queue RAM

- SRAM used as USB endpoint buffer, access is arbitrated by IQUE module

• 8-channel Timer (TIM)

– Eight input capture/output compare channels

– Clock prescaling

– 16-bit counter

– 16-bit pulse accumulator

• Serial Interface

– Asynchronous serial communication interface (SCI)

• Internal Regulator (VREG_U)

– Input voltage range from 4.25V to 5.5V

– Separate Regulation circuits

- 2.5V Regulator for Core Logic and memory

- 3.3V Regulator for USB2.0 physical layer interface

- 3.3V Regulator with off-chip NMOS driver for I/O and memory cards

– Power on Reset detection

• Integrated Queue Controller (IQUE)

– Provide block data transfer without CPU intervention

– Four independent queue channels for data transfer between Queue RAM and peripherals

– Unified Queue RAM Memory which can be allocated to different usb endpoints and storage interface module

– Programming model allows implementation of double buffering for maximum burst data throughput of 60M bytes per second between USB20D6E2F and one of the Storage Interfaces

• Universal Serial Bus 2.0 (USB20D6E2F)

– Intergrated USB2.0 Physical Layer Transceiver (USB20PHY) for High speed and Full Speed operations

– USB 2.0 Serial Interface Engine (USB20SIE) for High Speed and Full Speed operations compatible

- Endpoint 0 for Control IN and OUT operation

- Endpoint 2 and 3 are configurable for Bulk, ISO or Interrupt IN/OUT operation

- Endpoint buffer with programmable size residing in Queue RAM for endpoints 4 and 5

- Endpoint 0 IN, endpoint 0 OUT, endpoint 2 and endpoint 3 each has an independent 64 bytes fixed endpoint buffer.

• ATA5 Host Controller Interface (ATA5HC)

– Support PIO mode 0 to 4

– Support Multi-word DMA mode 0 to 2

– Support UDMA mode 0 to 4 (Up to 60M Bytes/sec at UDMA mode 4)

– Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module

• Compact Flash Host Controller Interface (CFHC)

– Support Compact Flash memory and I/O mode access operations per CFA specification 1.4

– Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module

• Secure Digital and Multimedia Card Host Controller Interface (SDHC)

– Compatible with the MMC System Specification Version 3.0

– Compatible with the SD Memory Card Specification 1.0

– Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module

• Smartmedia Host Controller Interface (SMHC)

– Compatible with SmartMedia Specification 1.0

– Support SmartMedia with memory size of 4M Bytes to 128M Bytes

– Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module

• Memorystick Host Controller Interface (MSHC)1

– Compatible with Memory Stick Standard 1.3

– Sector data can be transferred to and from USB endpoint buffer without CPU intervention using IQUE module

• Two Asynchronous External Interrupt pins

– XIRQ

– IRQ2

• 100-Pin LQFP package

– Up to 6 I/O pins with 5V only drive capability and 2 input only 5V pins.

– Up to 67 I/O pins with 3.3V/5V input and drive capability.

• 64-Pin LQFP package

– User selectable subset of modules available.

– Up to 6 I/O pins with 5V only drive capability and 1 input only 5V pin.

– Up to 35 I/O pins with 3.3V/5V input and drive capability.

• Operating frequency

– Maximum 60MHz equivalent to 30MHz CPU Bus Speed for single chip modes.

– 60MHz operation for IQUE module and storage interface modules attached to IQUE.