MC92610中文资料Quad 3.125 Gbaud SerDes Transceivers数据手册恩XP规格书

描述 Description

Overview The MC92610 Quad is a high-speed, full-duplex, serializer/deserializer (SerDes) data interface that can be used to transmit data between chips across a board, through a backplane, or through cabling. Four transceivers transmit and receive coded data at a rate of 2.5 gigabit per second (Gbps) through each 3.125 gigabaud link. A rich feature set makes it easily adaptable to many broadband applications. The 3.125 Gig Quad is the latest generation in the SerDes product line. Like it's predecessors, it features a very low power CMOS implementation that nominally consumes less than 1800mW with all links operating at full speed.

特性 Features

Product Highlights



•Four full-duplex differential data links


•20 Gbps data aggregate transfer speed


•Dual speed range: 3.125 Gbaud or 1.25 Gbaud


•Low power: 1800mW, under typical conditions, with all transceivers operating at full speed


•Transceiver channels may be individually disabled


•IEEE Std. 1149.1 JTAG support and full-speed built-in self test, BIST, functions



Data Interface



•Internal Fibre Channel 8B/10B encoder/decoder accessed through Byte Interface or bypassed in Ten-Bit Interface mode


•Double data rate (DDR), source synchronous, 8-bit and 10-bit HSTL parallel data interfaces


•Link Multiplex Mode enables operation of two links with single data rate (SDR), source synchronous, 16-bit and 20-bit parallel data interfaces


•Selectable Idle character alignment mode enables transfers with automatic realignment or unaligned data transfers


•Link-to-link synchronization supports aligned, 32-bit, word transfers. Synchronization mechanism tolerates up to 40-bit times of link-to-link media delay skew


•Multi-chip link synchronization supports aligned multi-word transfers. Up to four devices may be ganged to provide 128-bit, four-word, synchronized transfers


•Each channel has dedicated input clock (


•Received data may be clocked at the recovered clock or the reference clock frequency



Link Interface



•Links drive 50 Ohm media (100 Ohm differential), backplane or cable


•On-chip link termination (no external terminating resistors needed)


•On-chip coupling capacitors provide expanded common mode range


•Link inputs are \"hot-swap\" compatible


•Selectable transmit and receive equalization


•Repeater mode configures the device into a four-link receive-transmit repeater


•Redundant transmitter link outputs and receiver link inputs


•Redundant links are selectable per transceiver


•Broadcast mode enables all transmit links






Typical Applications


High-speed data transfer applications in high-bandwidth backplane and chassis-to-chassis networking.


•High-end router systems


•Backbone switches


•Storage Area Network equipment


•High-speed Automatic Test Equipment



Technical Specifications



•All channels have:


•8B/10B encoder/decoder that can be enabled or bypassed


•Clock generation/recovery


•Independent 8-bit or 10bit system I/F with parallel-to-serial, serial-to-parallel conversion


•Idle/control character generation/detection





•Transceiver Links operate over 50 Ohm media(100 Ohm differential) for lengths of up to 1 meters of FR-4 board/back-plane, or six meters of coax


•No external loop filter components required


•In-system BIST test modes


•At speed, in circuit, with error counter


•Loopback BIST isolated from link inputs and outputs





•IEEE Std. 1149.1 JTAG boundary scan support


•Differential reference clock input with single-ended reference clock input option (156.25 MHz max)


•Tolerates REF_CLK frequency offset in excess of +- 200ppm