MC88LV915T集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

The MC88LV915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations.

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88LV915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88LV915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 4 on Page 9).

Features

• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps

each being phase and frequency locked to the SYNC input

• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is

less than 550 ps (derived from the tPD specification, which defines the part–to–part skew)

• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

• Input frequency range from 5MHz – 2X_Q FMAX spec.

• Additional outputs available at 2X and +2 the system “Q” frequency.

Also a Q (180° phase shift) output available

• All outputs have ±36 mA drive (equal high and low) at CMOS levels,

and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible. ±88mA IOL/IOH

specifications guarantee 50Ω transmission line switching on the incident edge

• Test Mode pin (PLL_EN) provided for low frequency testing.

Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3–state) for board test purposes

• Lock Indicator (LOCK) accuracy indicates a phase–locked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.