MC74LCX16244数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The MC74LCX16244 is a high performance, non-inverting 16-bit buffer operating from a 2.3 to 3.6V supply. The device is nibble controlled. Each nibble has separate Output Enable inputs which can be tied together for full 16-bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX16244 inputs to be safely driven from 5V devices.The MC74LCX16244 is suitable for memory address driving and all TTLlevel bus oriented transceiver applications.The 4.5ns maximum propagation delays support high performance applications. Current drive capability is 24mA at the outputs. The Output Enable (OEn)bar inputs, when HIGH, disable the outputs by placing them ina HIGH Z condition.The MC74LCX16244 contains sixteen non-inverting buffers with 3-state 5V-tolerant outputs. The device is nibble controlled with each nibble functioning identically, but independently. The control pins may be tied together to obtain full 16-bit operation. The 3-state outputs are controlled by an Output Enable (OEn)bar input for each nibble. When OEnbar is LOW, the outputs are on. When OEnbar is HIGH, the outputs are in the high impedance state.

特性 Features

• Designed for 2.3 to 3.6V VCC Operation
• 4.5ns Maximum tpd
• 5V Tolerant - Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20mA) Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V;Machine Model >200V
• These are Pb-Free Devices

简介

MC74LCX16244属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的MC74LCX16244缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。