Octal D Flip?묯lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：122.9 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Package：20-DIP（0.300"，7.62mm）；包装：卷带（TR） 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20DIP

ONSEMI

安森美半导体

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体