Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

文件：225.76 Kbytes 页数：9 Pages

ONSEMI

安森美半导体