Octal D Flip?묯lop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：122.9 Kbytes 页数：10 Pages

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Octal D Flip-Flop with Clock Enable

文件：102.21 Kbytes 页数：9 Pages

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Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 8BIT 20SOIC

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安森美半导体

Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：111.52 Kbytes 页数：12 Pages

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安森美半导体

Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：111.52 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Octal D Flip-Flop with Clock Enable

The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time be

文件：111.52 Kbytes 页数：12 Pages

ONSEMI

安森美半导体