MC68PM302PV16中文资料恩智浦数据手册PDF规格书

FEATURES

The features of the MC68PM302 are as follows. The items in bold face type show major differences from the MC68302. • On-Chip Static 68000 Core Supporting a 16-or 8-Bit M68000 Family-System • SIB Including: - Independent Direct Memory Access (IDMA) Controller. - Interrupt Controller with Two Modes of Operation -Parallel Input/Output (I/O) Ports, Some with Interrupt Capability -On-Chip 1152-Byte Dual-Port RAM -Three Timers Including a Watchdog Timer - New Periodic Interrupt Timer (PIT) - Four Programmable Chip-Select Lines with Wait-State Generator Logic - Programmable Address Mapping of the Dual-Port RAM and IMP Registers -On-Chip Clock Generator with Output Signal - Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM - Allows Boot in 8-Bit Mode, and Running Switch to 16-Bit Mode - Allows System Clock to be Generated from 32 kHz or 4 MHz crystals in Addition to a Full Speed Clock Oscillator -System Control: System Status and Control Logic Disable CPU Logic (Slave Mode Operation) Hardware Watchdog New Low-Power (Standby) Modes in μA Range With Wake-up from Two Pins or PIT Timer Freeze Control for Debugging DRAM Refresh Controller -CP Including: - Main Controller (RISC Processor) -Three Independent Full-Duplex Serial Communications Controllers (SCCs) - Supporting Various Protocols: High-Level/Synchronous Data Link Control (HDLC/SDLC) Universal Asynchronous Receiver Transmitter (UART) Binary Synchronous Communication (BISYNC) Transparent Modes Autobaud Support Instead of DDCMP V.110 Rate Adaption -Six Serial DMA Channels for the Three SCCs - Flexible Physical Interface Accessible by SCCs Including ISDN Support:

Motorola Interchip Digital Link (IDL) General Circuit Interface (GCI, also known as IOM-2¹) Pulse Code Modulation (PCM) Highway Interface Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals SCP for Synchronous Communication -Two Serial Management Controllers (SMCs) To Support IDL and GCI Auxiliary Channels PCMCIA Controller - Supports Slave Interface Having 8 or 16-bit Data Pins - Compatible with the PC Card Classic Specification Approved in October 1994 - Support for Ring Detect and Other Indications - Support for Power Down Modes and Automatic Wakeup on Host Access - Card Information Structure (CIS) Size and Location In Memory Programmable - Supports DMA Accesses as Defined by PCMCIA - Supports DMA Direct Access to Common Memory Space for High Speed Buffer Transfers - Security Option to Prevent Host Accesses to Sensitive Address Ranges - Separate PCMCIA Reset Signal • 16550 Emulation Block - Complete H/W and S/W Emulation of the 16550 UART - DMA Supported for Transfer of 16550 Data Over 68K Bus - Speed of Data Transfer Can Be Matched to Traditional 16550 UART - High Speed Data Transfer up to 2 Mbps Possible • Initial Offering Features 16.67 and 20 MHz Versions at 5V and 3.3V 144 Pin Thin Quad Flat Pack (TQFP) Packaging