MC68MH360CAI25L数据手册恩XP中文资料规格书

描述 Description

The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications.
The MC68360 particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term \"quad\" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

特性 Features

CPU+ Processor (8.3 MIPS at 33MHz)
• 32-bit version of the CPU32 core (fully compatible with CPU32)
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
• Complete static design (0-33 MHz Operation)
• Slave mode to disable CPU32+ (allows use with external processors)
• Multiple QUICCs can share one system bus (one master)
• MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz)
• All QUICC features available in slave mode
• Memory controller (eight banks)
• Contains complete Dynamic Random-Access Memory (DRAM) controller
• Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM),
• Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
• Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory)
• Special features for MC68040 including Burst Mode
• Four general-purpose timers
• Four 16-bit timers or two 32-bit timers
• Two Independent DMAs (IDMAs)
• System Integration Module (SIM60)
• Bus monitor
• Breakpoint logic provides on-chip H/W breakpoints
• Spurious interrupt monitor
• External masters may use on-chip features such as chip selects
• Periodic interrupt timer
• On-chip bus arbitration with no overhead for internal masters
• Low power stop mode
• IEEE 1149.1 Test Access Port
• RISC Communications Processor Module (CPM)
• Many new commands (e.g., Graceful Stop Transmit, Close RxBD)
• Supports continuos mode transmission and reception on all serial channels
• 2.5 kbytes of dual-port RAM
• 14 Serial DMA (SDMA) channels
• Three parallel I/O registers with open-drain capability
• Each serial channel can have its own Pins (NMSI mode)
• Four baud rate generators
• Four SCCs
• Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz
• HDLC Bus
• Universal Asynchronous Receiver Transmitter (UART)
• Synchronous UART
• Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point Protocol)
• Two SMCs
• UART
• Transparent
• General Circuit Interface (GCI) controller
• One SPI
• Time-Slot assignor
• Supports two TDM channels
• Parallel Interface Port (supports fast connection between QUICCs)