MC68HRC705JP7CDW中文资料摩托罗拉数据手册PDF规格书

General Description

Introduction

The Motorola MC68HC705JJ7 and MC68HC705JP7 are erasable programmable read-only memory (EPROM) versions of the MC68HC05JJ/JP Family of microcontrollers (MCU).

Features

Features of the two parts include:

• Low-cost, M68HC05 core MCU in 20-pin package (MC68HC705JJ7) or 28-pin package (MC68HC705JP7)

• 6160 bytes of user EPROM, including 16 bytes of user vectors

• 224 bytes of low-power user random-access memory (RAM)

• 64 bits of personality EPROM (serial access)

• 16-bit programmable timer with input capture and output compare

• 15-stage core timer, including 8-bit free-running counter and 4-stage selectable real-time interrupt generator

• Simple serial input/output port (SIOP) with interrupt capability

• Two voltage comparators, one of which can be combined with the 16-bit programmable timer to create a 4-channel, single-slope analog-to-digital (A/D) converter

• Output of voltage comparator can drive port pin PB4 directly under software control

• 14 input/output (I/O) lines (MC68HC705JJ7) or 22 I/O lines (MC68HC705JP7), including high-source/sink current capability on 6 I/O pins (MC68HC705JJ7) or 14 I/O pins (MC68HC705JP7)

• Programmable 8-bit mask option register (MOR) to select mask options found in read-only memory (ROM) based versions

• MOR selectable software programmable pulldowns on all I/O pins and keyboard scan interrupt on four I/O pins

• Software mask and request bit for IRQ interrupt with MOR selectable sensitivity on IRQ interrupt (edge- and level-sensitive or edge-only)

• On-chip oscillator with device option of crystal/ceramic resonator or resistor-capacitor (RC) operation and MOR selectable shunt resistor, 2 MΩ by design

• Internal oscillator for lower-power operation, approximately 100 kHz (500 kHz selected as device option)

• EPROM security bit(1) to aid in locking out access to programmable EPROM array

• MOR selectable computer operating properly (COP) watchdog system

• Power-saving stop and wait mode instructions (MOR selectable STOP conversion to halt and option for fast 16-cycle restart and power-on reset)

• On-chip temperature measurement diode

• MOR selectable reset module to reset central processor unit (CPU) in low-voltage conditions

• Illegal address reset

• Internal steering diode and pullup device on RESET pin to VDD