MC68HC912DT128P中文资料恩智浦数据手册PDF规格书

Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to

M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow modes

• Memory

– 128K byte flash EEPROM, made of four 32K byte modules

with 8K bytes protected BOOT section in each module

– 2K byte EEPROM

– 8K byte RAM with Vstby, made of two 4K byte modules.

• Two Analog-to-digital converters

– 2 times 8-channels, 10-bit resolution

• Three 1M bit per second, CAN 2.0 A, B software compatible

modules on the MC68HC912DT128A (two on the

MC68HC912DG128A)

– Two receive and three transmit buffers per CAN

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

per CAN

– Low-pass filter wake-up function

– Loop-back for self test operation

– Programmable link to a timer input capture channel, for timestamping

and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4

of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on

four channels, or two captures on four channels with a

capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of

frequencies

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– Inter IC bus interface (I2C)

– Synchronous serial peripheral interface (SPI)

• LIM (lite integration module)

– WCR (windowed COP watchdog, real time interrupt, clock

monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MMI (memory map and interface)

– INT (interrupt control)

– BKP (breakpoints)

– BDM (background debug mode)

• Two 8-bit ports with key wake-up interrupt

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

– Option of a Pierce or Colpitts oscillator

• 112-Pin TQFP package

– Up to 67 general-purpose I/O lines on the

MC68HC912DT128A (up to 69 on the MC68HC912DG128A),

plus up to 18 input-only lines

– 5.0V operation at 8 MHz

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints