MC68HC912BL16TS/D中文资料恩智浦数据手册PDF规格书

Features

• 16-Bit CPU12

— Upward Compatible with M68HC11 Instruction Set

— Interrupt Stacking and Programmer’s Model Identical to M68HC11

— 20-Bit ALU

— Instruction Queue

— Enhanced Indexed Addressing

— Fuzzy Logic Instructions

• Multiplexed Bus

— Single Chip or Expanded

— 16/16 Wide or 16/8 Narrow Modes

• Memory

— 16-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block

— 512-byte EEPROM

— 512-byte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write

• 8-Channel, 10-bit Analog-to-Digital Converter

• 7-Channel Timer

— Each Channel Fully Configurable as Either Input Capture or Output Compare

— Simple PWM Mode

— Modulo Reset of Timer Counter

• 16-Bit Pulse Accumulator

— External Event Counting

— Gated Time Accumulation

• Pulse-Width Modulator

— 8-Bit, 4-Channel or 16-Bit, 2-Channel

— Separate Control for Each Pulse Width and Duty Cycle

— Programmable Center-Aligned or Left-Aligned Outputs

• Serial Interfaces

— Asynchronous Serial Communications Interface (SCI)

— Synchronous Serial Peripheral Interface (SPI)

• COP Watchdog Timer, Clock Monitor, and Periodic Interrupt Timer

• 64-Pin QFP Package

— Up to 49 General-Purpose I/O Lines

— 4.5V–5.5V Operation at 8 MHz

• Single-Wire Background Debug™ Mode (BDM)

• On-Chip Hardware Breakpoints