MC68HC705J2P数据手册恩XP中文资料规格书

描述 Description

INTRODUCTION
The MC68HC705J2 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The high-density, complementary metal-oxide semiconductor (HCMOS) M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types.
The MC68HC705J2 is an expansion of the MC68HC05J1 design. On-chip memory is enhanced with 2 Kbytes of erasable, programmable ROM (EPROM), 112 Kbytes of RAM, and a bootloader ROM.

特性 Features

The MCU features include the following:
• Popular M68HC05 CPU
• Memory-Mapped Input/Output (I/O) Registers
• 2064 Bytes of User EPROM Including 16 User Vector Locations
• 112 Bytes of Static RAM (SRAM)
• 14 Bidirectional I/O Pins
• Fully Static Operation With No Minimum Clock Speed
• On-Chip Oscillator With Crystal/Ceramic Resonator Connections
• 15-Bit Multifunction Timer
• Real-Time Interrupt Circuit
• Bootloader ROM
• Power-Saving STOP, WAIT, and Data Retention Modes
• MC68HC05J1 Emulation Mode
• Selectable Edge-Sensitive or Edge- and Level-Sensitive External Interrupt Trigger
• Selectable Computer Operating Properly (COP) Timer
• 8 x 8 Unsigned Multiply Instruction
• One Time Programmable 20-Pin Dual-in-Line Package (DIP)
• One Time Programmable 20-Pin Small Outline Integrated Circuit (SOIC)
• Windowed 20-Pin Cerdip