MC68HC08AS32SLASHD中文资料恩智浦数据手册PDF规格书

Features

Features include:

• High-performance M68HC08 architecture

• Fully upward-compatible object code with M6805, M146805, and M68HC05

Families

• 8.4-MHz internal bus frequency

• 32,256 bytes of read-only memory (ROM)

• ROM data security

• 512 bytes of on-chip electrically erasable programmable read-only memory

(EEPROM)

• 1024 bytes of on-chip random-access memory (RAM)

• Serial peripheral interface module (SPI)

• Serial communications interface module (SCI)

• 16-bit, 6-channel timer interface module (TIM)

• Clock generator module (CGM)

• 8-bit, 15-channel analog-to-digital converter module (ADC)

• SAE J1850 byte data link controller digital module (BDLC-D)

• System protection features:

– Computer operating properly (COP) with optional reset

– Low-voltage detection with optional reset

– Illegal opcode detection with optional reset

– Illegal address detection with optional reset

• Low-power design (fully static with stop and wait modes)

• Master reset pin and power-on reset

Features of the CPU08 include:

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (eight more than the HC05)

• 16-bit index register and stack pointer

• Memory-to-memory data transfers

• Fast 8 × 8 multiply instruction

• Fast 16/8 divide instruction

• Binary-coded decimal (BCD) instructions

• Optimization for controller applications

• C language support