MC68E360VR25VL中文资料QUICC, ETHRN数据手册恩XP规格书

描述 Description

The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications.
The MC68360 particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term \"quad\" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

特性 Features

CPU+ Processor (8.3 MIPS at 33MHz)
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
• Slave mode to disable CPU32+ (allows use with external processors)
• Multiple QUICCs can share one system bus (one master)
• All QUICC features available in slave mode
• Contains complete Dynamic Random-Access Memory (DRAM) controller
• Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
• Special features for MC68040 including Burst Mode
• Four 16-bit timers or two 32-bit timers
• System Integration Module (SIM60)
• Bus monitor
• Spurious interrupt monitor
• Periodic interrupt timer
• Low power stop mode
• RISC Communications Processor Module (CPM)
• Many new commands (e.g., Graceful Stop Transmit, Close RxBD)
• 2.5 kbytes of dual-port RAM
• Three parallel I/O registers with open-drain capability
• Four baud rate generators
• Ethernet/IEEE 802.3 optional on SCCs 1-2@25 MHz, SCCs 1-3@33 MHz
• Universal Asynchronous Receiver Transmitter (UART)
• Asynchronous HDLC (RAM microcode option) to support PPP (Point to Point Protocol)
• UART
• General Circuit Interface (GCI) controller
• Time-Slot assignor
• Parallel Interface Port (supports fast connection between QUICCs)