MC56F8366中文资料飞思卡尔数据手册PDF规格书

56F8366/56F8166 General Description

• Up to 60 MIPS at 60MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• Access up to 1MB of off-chip program and data memory

• Chip Select Logic for glueless interface to ROM and SRAM

• 512KB of Program Flash

• 4KB of Program RAM

• 32KB of Data Flash

• 32KB of Data RAM

• 32KB of Boot Flash

• Up to two 6-channel PWM modules

• Four 4-channel, 12-bit ADCs

• Temperature Sensor

• Up to two Quadrature Decoders

• Optional On-Chip Regulator

• Up to two FlexCAN modules

• Two Serial Communication Interfaces (SCIs)

• Up to two Serial Peripheral Interfaces (SPIs)

• Up to four General Purpose Quad Timers

• Computer Operating Properly (COP) / Watchdog

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 62 GPIO lines

• 144-pin LQFP Package

56F8366/56F8166 Features

Core

• Efficient 16-bit 56800E family controller engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface