MC54HC74AJ中文资料DUAL D FLIP-FLOP WITH SET AND RESET数据手册恩XP规格书

描述 Description

DUAL D FLIP-FLOP WITH SET AND RESET
High–Performance Silicon–Gate CMOS

TheMC54/74HC74A is identical in pinout to the LS74. The device inputs arecompatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Thisdevice consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information at a D–input is transferred to the corresponding Q outputon the next positive going edge of the clock input. BothQ and Q
outputsare available from each flip–flop. The Set and Reset inputs are asynchronous.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 128 FETs or 32 Equivalent Gates