BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER

The MC14511B BCD−to−seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4−bit storage latch, an 8421 BCD−to−seven segment decoder, and an ou

文件：130.24 Kbytes 页数：9 Pages

Motorola

摩托罗拉

18-BIT STATIC SHIFT REGISTER

The MC14006B shift register is comprised of four separate shift register sections sharing a common clock: two sections have four stages, and two sections have five stages with an output tap on both the fourth and fifth stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12

文件：108.85 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Industrial Time Base Generator

The MC14566B industrial time base generator is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. This device consists of a divide–by–10 ripple counter and a divide–by–5 or divide–by–6 ripple counter to permit stable time generation from a 50 or

文件：200.11 Kbytes 页数：8 Pages

Motorola

摩托罗拉

QUAD TRANSPARENT LATCH

The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches c

文件：202.87 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Hex Non-Inverting 3-State Buffer

The MC14503B is a hex non–inverting buffer with 3–state outputs, and a high current source and sink capability. The 3–state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go

文件：214.72 Kbytes 页数：6 Pages

Motorola

摩托罗拉

4x4 Multiport Register

4 x 4 Multiport Register The MC14580B is a 4 by 4 multiport register useful in small scratch pad memories, arithmetic operations when coupled with an adder, and other data storage applications. It allows independent reading of any two words (or the same word at both outputs) while writing into an

文件：234.26 Kbytes 页数：7 Pages

Motorola

摩托罗拉

Dual 4?밒nput ?쏯AND??Gate 2?밒nput ?쏯OR/OR??Gate 8?밒nput ?쏛ND/NAND??Gate

Dual 4–Input “NAND” Gate 2–Input “NOR/OR” Gate 8–Input “AND/NAND” Gate The MC14501UB is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immuni

文件：222.85 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Phase Comparator and Programmable Counters

The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or 100 counter and a programmable divide–by–N 4–bit binary counter (all positive–edge triggered) constructed with MOS P–channelandN–channel enhancement mode devices (complementary MOS) in a monolithic structure. TheMC14568B has bee

文件：326.07 Kbytes 页数：12 Pages

Motorola

摩托罗拉

BCD Up/Down Counter

The MC14510B synchronous up/down BCD counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide type T flip–flop capability. This counter can be preset by applying t

文件：284.42 Kbytes 页数：10 Pages

Motorola

摩托罗拉

NBCD Adder

NBCD Adder The MC14560B adds two 4–bit numbers in NBCD (natural binary coded decimal) format, resulting in sum and carry outputs in NBCD code. This device can also subtract when one set of inputs is complemented with a 9’s Complementer (MC14561B). All inputs and outputs are active high. The car

文件：310.03 Kbytes 页数：13 Pages

Motorola

摩托罗拉