MC145576中文资料ISDN Single-Chip NT1数据手册恩XP规格书

描述 Description

Overview The ISDN Single-Chip NT1 offers the most cost-effective solution for the design of Network Termination Equipment. It has a flexible interface, making it compatible with other NXP® ISDN components. When combined with Our controller family, the MC145576 becomes the heart of a powerful and cost-effective Smart NT1 solution. The MC145576 integrated NT1 fully complies with the appropriate USA and European recommendations for the U-interface -- ANSI T1.601 1992, ETSI ETR 080, FT CS3211 in NT mode -- and the S/T-interface -- ITU I.430, ANSI T1.605, ETSI ETS 300 012 in NT mode. The U-interface uses 2B1Q line coding. The device offers both GCI and IDL/SCP interfaces for compatibility with previous designs based upon the MC145574A S/T-Interface Transceiver and the MC145572 U-Interface Transceiver chip set. The SCP serial interface allows connection to the extensive family of NXP controllers. When combined with a member of the MC68302 family of multiprotocol controllers, MC145484 PCM codec, and an analog line interface (SLIC), the MC145576 enables optimal design of a Smart NT1 or a Smart Terminal Adapter (U-interface based TA with an S/T bus access). The same architecture can be used with a second codec and SLIC to allow for a dual analog interface design.

特性 Features

•Fully-conformant U- and S/T-interfaces, meets and exceeds all
loop performance requirements according to U.S. and European
standards

•U-interface: ANSI T1.601 1992, ETSI ETR 080, FT CS3211
•S/T-interface: ITU I.430, ANSI T1.605, ETSI ETS 300 012

•Supports micro-linebreaks per ETSI standard
•Flexible system interface, pin-selectable (IDL+SCP) or GCI
interface
•NT terminal interface
•Fully-automatic activation in GCI mode
•Automatic handling of basic maintenance functions
•Warm start capability
•NT synchronizes to and operates with 80 kHz +/-32 ppm received
signal from LT
•Automatic internal compliance with Embedded Operation Channel
(EOC) Protocol, as specified in ANSI and ETSI standards
•Dedicated pins for

•Pulse test signal generation
•Power Mode Select PS 1/2
•Fixed/adaptive timing selection for S bus
•Loopback active
•LED activation

•Complete set of loopbacks
•Low power consumption (250 mW typical)
•Single 5 V power supply
•S and Q multiframe capability via external microcontroller
connection
•High-performance CMOS process technology
•Compatible with 3 V devices