MC14526B数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The MC14526B binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded \"0\" state output for divide-by-N applications. In single stage applications the \"0\" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.

特性 Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge-Clocked Design - Incremented on Positive Transition of Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
• Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
• Pb-Free Packages are Available

简介

MC14526B属于集成电路（IC）的计数器除法器。由制造生产的MC14526B计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。