Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

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CMOS LSI (LOW-POWER COMPLEMENTARY MOS) 3 1/2 DIGIT A/D CONVERTER

CMOS LSI(LOW-POWER COMPLEMENTARY MOS) 3 1/2 DIGIT A/D CONVERTER

文件：450.58 Kbytes 页数：12 Pages

MOTOROLA

摩托罗拉

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

文件：96.4 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad Type D Flip?묯lop

文件：123.91 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

Quad Type D Flip-Flop

文件：128.169 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

Quad Type D Flip?묯lop

文件：123.91 Kbytes 页数：6 Pages

ONSEMI

安森美半导体