MC10H641数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The MC10H/100H641 is a single supply, low skew translating 1:9 clock driver. Devices in the H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The device features a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. Both the LEN and EN pins are positive ECL inputs. The VBB output is provided in case the user wants to drive the device with a single-ended input. For single-ended use the VBB should be connected to the D input and bypassed with a 0.01 F capacitor. The 10H version of the H641 is compatible with positive MECL 10H logic levels. The 100H version is compatible with positive 100K levels.

特性 Features

PECL-TTL Version of Popular ECLinPS E111
Low Skew
Guaranteed Skew Spec
Latched Input
Differential ECL Internal Design
VBB Output for Single-Ended Use
Single +5V Supply
Logic Enable
Extra Power and Ground Supplies
Separate ECL and TTL Supply Pins
Pb-Free Packages are Available

简介

MC10H641属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的MC10H641时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。