MC10EP33DR2集成电路（IC）的计数器除法器规格书PDF中文资料

MC10EP33DR2属于集成电路（IC）的计数器除法器。由安森美半导体公司制造生产的MC10EP33DR2计数器，除法器计数器和除法器 IC 是数字逻辑器件，可对输入发生的逻辑转换进行计数，然后使用多个并行输出重新发送累加的计数，和/或生成单个输出信号转换，从而对应用某些整数数量输入信号转换进行响应。除了简单的事件计数，它们还可用于各种频率合成应用。

Description

The MC10/100EP33 is an integrated ÷4 divider. The differential clock inputs.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The reset pin is asynchronous and is asserted on the rising edge. Upon powerup, the internal flip−flops will attain a random state; the reset allows for the synchronization of multiple EP33’s in a system.

The 100 Series contains temperature compensation.

Features

• 320 ps Propagation Delay

• Maximum Frequency > 4 GHz Typical

• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at VEE

• VBB Output

• Pb−Free Packages are Available