3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a pos

文件：73.45 Kbytes 页数：8 Pages

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安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset

文件：173.36 Kbytes 页数：11 Pages

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安森美半导体

ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

文件：111.13 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3 V / 5.0 V ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transitio • Maximum Frequency > 3 GHz Typical\n• 500 ps Typical Propagation Delays\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• These are Pb−Free Devices;

ONSEMI

安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a pos

文件：73.45 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a pos

文件：73.45 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset

文件：173.36 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

文件：111.13 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset

文件：173.36 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset

文件：173.36 Kbytes 页数：11 Pages

ONSEMI

安森美半导体