MC10EP131中文资料3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock数据手册ONSEMI规格书

描述 Description

The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and (CCbar) HIGH, then using the Clock Enable inputs for clocking (C0-3 and C0-3bar).Common clocking is achieved by holding the C0-3 inputs LOW and C0-3bar inputs HIGH while using the differential common clock CC to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.Individual asynchronous resets (R0-3) and an asynchronous set (SET) are provided.Data enters the master when both CC and C0-3 are LOW, and transfers to the slave when either CC or C0-3 (or both) go HIGH.The 100 Series contains temperature compensation.

特性 Features

• 460ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• Differential Individual and Common Clocks
• Individual Asynchronous Resets
• Asynchronous Set
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output will default LOW with inputs open or at VEE
• Pb-Free Packages are Available

应用 Application

• High Performance Logic for test systems

简介

MC10EP131属于集成电路（IC）的触发器。由制造生产的MC10EP131触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。