첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

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安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

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安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes 页数：8 Pages

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安森美半导体

Clock Generation Chip

文件：173.77 Kbytes 页数：9 Pages

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安森美半导体

5.0 V ECL ÷·2，÷·4，÷·8 时钟生成芯片

The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by ei • 50ps Output-to-Output Skew\n• Synchronous Enable/Disable\n• Master Reset for Synchronization\n• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\n• Internal Input Pulldown Resistors on CLK(s), ENbar, and MR\n• Pb-Fre;

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安森美半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：69.23 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

5V ECL 첨2, 첨4, 첨8 Clock Generation Chip

文件：133.17 Kbytes 页数：8 Pages

ONSEMI

安森美半导体