Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

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Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

文件：110.45 Kbytes 页数：4 Pages

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安森美半导体

Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

文件：110.45 Kbytes 页数：4 Pages

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安森美半导体

Dual 4 to 1 Multiplexer

The MC10174 is a high speed dual channel multiplexer with output enable capability. The select inputs determine one of four active data inputs for each multiplexer. An output enable forces both outputs low when in the high state. • PD = 305 mW typ/pkg (No Load) • tpd = 3.5 ns typ (Dta to ou

文件：110.45 Kbytes 页数：4 Pages

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Quint Latch

The MC10175 is a high speed, low power quint latch. It features five D type latches with common reset and a common two–input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are “OR”ed together. Any change on the data input will b

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Hex D Master/Slave Flip-Flop

Hex D Master/Slave Flip-Flop The MC10176 contains six high-speed, master slave type “D” flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may

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Binary Counter

The MC10178 is a four–bit counter capable of divide–by–two, divide–by–four, divide–by–eight or a divide–by–sixteen function. Clock inputs trigger on the positive going edge of the clock pulse. Set and Reset inputs override the clock, allowing asynchronous “set” or “clear.” Individual Set and comm

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Dual Binary to 1-4 Decoder (Low)

文件：112.48 Kbytes 页数：8 Pages

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Dual Binary to 1-4 Decoder (Low)

文件：112.48 Kbytes 页数：8 Pages

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安森美半导体

Dual Binary to 1-4 Decoder (Low)

文件：112.48 Kbytes 页数：8 Pages

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安森美半导体