Triple D Flip-Flop With Set and Reset

Description The MC100LVEL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided fo

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3.3V ECL Triple D Flip?묯lop with Set and Reset

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ECL Triple D-Type Flip-Flop with Set and Reset

The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the MC100LVEL30 but is specified for operation at the standard 100E ECL voltage supply. Data enters the master latch when the clock input is LOW and transfers to the sl • 1200MHz Minimum Toggle Frequency\n• 450 ps Typical Propagation Delays\n• ESD Protection: >2 KV HBM\n• The 100 Series Contains Temperature Compensation.\n• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V\n• Internal ;

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3.3V ECL Triple D Flip?묯lop with Set and Reset

文件：114.07 Kbytes 页数：6 Pages

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ECL Triple D Flip?륡lop with Set and Reset

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3.3V ECL Triple D Flip?묯lop with Set and Reset

文件：114.07 Kbytes 页数：6 Pages

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安森美半导体

ECL Triple D Flip?륡lop with Set and Reset

文件：145.22 Kbytes 页数：6 Pages

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安森美半导体

3.3V ECL Triple D Flip?묯lop with Set and Reset

文件：114.07 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

3.3V ECL Triple D Flip?묯lop with Set and Reset

文件：114.07 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

3.3V ECL Triple D Flip?묯lop with Set and Reset

文件：114.07 Kbytes 页数：6 Pages

ONSEMI

安森美半导体