MC100EP33

3.3V 5VECL / 4 Divider

Description TheMC10/100EP33isanintegrated÷4divider.Thedifferentialclockinputs. TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBBasaswitchingreferencevoltage.V

MC100EP33

Clock Management Design Using Low Skew and Low Jitter Devices

WhyDoWeNeedClockManagement? CanyouimaginethechaosinourworldifourclocksorwatcheswerenotsynchronizedtoGreenwichMeanTime?Howwouldtrains,buses,andairplanesrunonschedule?TheminiseriesLongitudewasthestoryofamanwhomadeamajortechnologicalbreakthroughbyinv

MC100EP33

3.3 V / 5.0 V ECL ÷·4 分频器; • 320ps Propagation Delay\n• Maximum Frequency > 4 GHz Typical\n• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Q Output will default LOW with inputs open or at VEE\n• VBB Output\n• Pb-Free Packages are Available\n;

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.The 100 Series contains temperature compensation.

MC100EP33

3.3V / 5V ECL 첨4 Divider

MC100EP33D

3.3V 5VECL / 4 Divider

Description TheMC10/100EP33isanintegrated÷4divider.Thedifferentialclockinputs. TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBBasaswitchingreferencevoltage.V

MC100EP33DR2

3.3V 5VECL / 4 Divider

Description TheMC10/100EP33isanintegrated÷4divider.Thedifferentialclockinputs. TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBBasaswitchingreferencevoltage.V

MC100EP33DT

3.3V 5VECL / 4 Divider

Description TheMC10/100EP33isanintegrated÷4divider.Thedifferentialclockinputs. TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBBasaswitchingreferencevoltage.V

MC100EP33DTR2

3.3V 5VECL / 4 Divider

Description TheMC10/100EP33isanintegrated÷4divider.Thedifferentialclockinputs. TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBBasaswitchingreferencevoltage.V

MC100EP33D

3.3V / 5V ECL 첨4 Divider

MC100EP33D

Evaluation Board Manual for High Frequency SOIC 8